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  EUA6204 ds6204 ver1.1 june. 2006 1 1.36-w mono fully differential audio power amplifier description the EUA6204 is a mono fully-differential audio amplifier, capable of delivering 1.36w of continuous average power to an 8 ? btl load with less than 1% distortion (thd+n) from a 5v power supply, and 720mw to a 8 ? load from a 3.6v power supply. the EUA6204 is ideal for pda/smart phone application due to features such as -80-db supply voltage rejection from 20ha to 2khz, improved rf rectification immunity, small 20mm 2 pcb area, and a fast startup with minimal pop. the EUA6204 is available in a msop-8 and in the space-saving 3mm ?? 3mm dfn package. typical application circuit features z supply voltage 2.5v to 5.5v z 1.36w into 8 ? from a 5-v supply at thd=1% (typ) z low supply current: 4ma typ at 5v z shutdown current: 0.01a typ z fast startup with minimal pop z only three external components - improved psrr (-80db) for direct battery operation - full differential design reduces rf rectification - -63db cmrr eliminates two input coupling capacitors z rohs compliant and 100% lead (pb)-free applications z wireless handsets z pdas z portable devices www.datasheet.in
EUA6204 ds6204 ver1.1 june. 2006 2 block diagram pin configurations package pin configurations dfn-8 msop-8 pin description symbol pin description shutdown 1 shutdown terminal bypass 2 mid-supply voltage, adding a bypass capacitor improves psrr in+ 3 positive differential input in- 4 negative differential input vo+ 5 positive btl output vdd 6 power supply gnd 7 high-current ground vo- 8 negative btl output www.datasheet.in
EUA6204 ds6204 ver1.1 june. 2006 3 ordering information order number package type marking operating temperature range EUA6204jir1 dfn-8 xxxx a6204 -40c to 85c EUA6204mir1 msop-8 xxxx a6204 -40c to 85c EUA6204 ?? ?? ?? ?? lead free code 1: lead free 0: lead packing r: tape & reel operating temperature range i: industry standard package type j: dfn m: msop www.datasheet.in
EUA6204 ds6204 ver1.1 june. 2006 4 absolute maximum ratings t supply voltage, v dd -------------------------------------------------------------------------------------------- 6v t input voltage, v i ---------------------------------------------------------------------------- -0.3 v to v dd +0.3v t storage temperature rang, t stg ------------------------------------------------------------------- -65c to 150c t esd susceptibility -------------------------------------------------------------------------------------------- 2kv t junction temperature -------------------------------------------------------------------------------------- 150c t thermal resistance jc (msop) ------------------------------------------------------------------------------------------- 56c/w ja (msop) ------------------------------------------------------------------------------------------- 160c/w ja (dfn) --------------------------------------------------------------------------------------------- 50c/w recommended operating conditions min nom max unit supply voltage, v dd 2.5 5.5 v high-level input voltage, v ih 1.55 v low-level input voltage, v il 0.5 operating free-air temperature, t a -40 85 c electrical characteristics, t a =25c EUA6204 symbol parameter conditions min t yp max. unit v os output offset voltage (measured differentially) v i =0v differential, gain=1v/v, v dd =5.5v -9 2 9 mv psrr power supply rejection ratio v dd =2.5v to 5.5v -85 -60 db v ic common mode input range v dd =2.5v to 5.5v 0.5 v dd -0.8 v v dd =2.5v, v ic =0.5v to 1.7v -63 -40 cmrr common mode rejection range v dd =5.5v, v ic =0.5v to 4.7v -63 -40 db v dd =5.5v 0.45 v dd =3.6v 0.37 low-output swing r l =8 ? , gain=1v/v v in+ =v dd , v in -=0v or v in+ =0v, v in -=v dd v dd =2.5v 0.26 0.4 v v dd =5.5v 4.95 v dd =3.6v 3.18 high-output swing r l =8 ? , gain=1v/v v in+ =v dd , v in -=0v or v in- =v dd , v in +=0v v dd =2.5v 2 2.13 v |i ih | high-level input current, shutdown v dd =5.5v, v i =5.8v 58 100 a |i il | low-level input current, shutdown v dd =5.5v, v i =-0.3v 3 100 a i q quiescent current v dd =2.5v to 5.5v, no load 4 8 ma i (sd) supply current v( shutdown ) 0.5v, v dd =2.5v to 5.5v, r l = 8 ? 0.01 1 a gain r l = 8 ? 38k ? ri 40k ? ri 42k ? ri v/v resistance from shutdown to gnd 100 k ? www.datasheet.in
EUA6204 ds6204 ver1.1 june. 2006 5 operating characteristics, t a =25c, gain=1v/v EUA6204 symbol parameter conditions min typ max. unit v dd =5v 1.36 v dd =3.6v 0.72 thd+n=1%, f=1khz,r l =8 ? v dd =2.5v 0.33 w v dd =5v 1.7 v dd =3.6v 0.85 p o output power thd+n=10%, f=1khz,r l =8 ? v dd =2.5v 0.4 w v dd =5v, p o =1w, r l =8 ? , f=1khz 0.15 v dd =3.6v, p o =0.5w, r l =8 ? , f=1khz 0.1 thd+n total harmonic distortion plus noise v dd =2.5v, p o =200mw, r l =8 ? , f=1khz 0.1 % f = 217hz -77 k svr supply ripple rejection ratio v dd =3.6v, inputs ac-grounded with c i =2f, v (ripple) =200mvpp f=20hz to 20khz -60 db snr signal-to-noise ratio v dd =5v, p o =1w, r l =8 ? 100 db no wei g htin g 25 vn output voltage noise v dd =3.6v, f=20hz to 20khz, inputs ac-grounded with c i =2f a wei g htin g 19 v rms cmrr common mode rejection ratio v dd =3.6v v ic =1vpp f=217hz -64 db r f feedback resistance 38 40 44 k ? start-up time from shutdown v dd =3.6v, c bypass =0.1f 27 ms www.datasheet.in
EUA6204 ds6204 ver1.1 june. 2006 6 typical operating characteristics www.datasheet.in
EUA6204 ds6204 ver1.1 june. 2006 7 www.datasheet.in
EUA6204 ds6204 ver1.1 june. 2006 8 www.datasheet.in
EUA6204 ds6204 ver1.1 june. 2006 9 application information application schematics figure14 through figure15 show application schematics for differential and single-ended inputs. typical values are shown in table1. table1. typical component value component value r i 40k ? c (bypass) 0.22f c s 1f c i 0.22f power dissipation power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or single-ended. a direct consequence of the increased power delivered to the load by a bridge amplifier is an increase in internal power dissipation. since the EUA6204 has two operational amplifiers in one package, the maximum internal power dissipation is 4 times that of a single-ended amplifier. the maximum power dissipation for a given application can be derived from the power dissipation graphs of from equation1. ------------(1) it is critical that the maximum junction temperature t jmax of 150c is not exceeded. t jmax can be determine from the power derating curves by using p dmax and the pc board foil area. by adding additional copper foil, the thermal resistance of the application can be reduced, resulting in higher p dmax. additional copper foil can be added to any of the leads connected to the EUA6204. if t jmax still exceeds 150c, then additional changes must be made. these changes can include reduced supply voltage, higher load impedance, or reduced ambient temperature. internal power dissipation is a function of output power. proper selection of external components gain-setting resistor selection the input resistor (r i ) can be selected to set the gain of the amplifier according to equation2. gain=r f /r i (2) the internal feedback resistors (r f ) are trimmed to 40k ? . resistor matching is very important in fully differential amplifiers. the balance of the output on the reference voltage depends on matched ratios of the resistors. cmrr, psrr, and the cancellation of the second harmonic distortion diminishes if resistor mismatch occurs. therefore, it is recommended to use 1% tolerance resistors or better to keep the performance optimized. bypass capacitor (c bypass ) and start-up time the internal voltage divider at the bypass pin of this device sets a mid-supply voltage for internal references and sets the output common mode voltage to v dd /2. adding a capacitor to this pin filters any noise into this pin and increases k svr. c (bypass) also determines the rise time of v o+ and v o- when the device is taken out of shutdown. the larger the capacitor, the slower the rise time. show the relationship of c (bypass) to start-up time as figure10. ) r /(2 ) (v * 4 p l dd dmax 2 2 = www.datasheet.in
EUA6204 ds6204 ver1.1 june. 2006 10 input capacitor (c i ) the EUA6204 does not require input coupling capacitors if using a differential input source that is biased from 0.5v to v dd -0.8v. use 1% tolerance or better gain-setting resistors if not using input coupling capacitors. in the single-ended input application an input capacitor, c i , is required to allow the amplifier to bias the input signal to the proper dc level. in this case, c i and r i form a high-pass filter with the corner frequency determined in equation3. (3) the value of c i is important to consider as it directly affects the bass (low frequency) performance of the circuit. consider the example where r i is 10k ? and the specification calls for a flat bass response down to 100hz. equation 3 is reconfigured as equation4. (4) in this example, c i is 0.16f, so one would likely choose a value in the range of 0.22f to 0.47f. ceramic capacitors should be used when possible, as they are the best choice in preventing leakage current. when polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most applications, as the dc level there is held at v dd /2, which is likely higher than the source dc level. it is important to confirm the capacitor polarity in the application. decoupling capacitor (c s ) the EUA6204 is a high-performance cmos audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (thd) is as low as possible. power supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. for higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (esr) ceramic capacitor, typically 0.1f to 1 f, placed as close as possible to the device v dd lead works best. for filtering lower frequency noise signals, a 10-f or greater capacitor placed near the audio power amplifier also helps, but is not required in most appli cations because of the high psrr of this device. i c i r 2 1 c f = c f i r 2 1 i c = www.datasheet.in
EUA6204 ds6204 ver1.1 june. 2006 11 package information dfn-8 note 1. all dimensions are in millimeters, is in degrees 2. m: the maximum allowable corner on the molded plastic body corner 3. dimension d does not include mold protrusions or gate burrs. mold protrusions and gate burrs shall not exceed 0.15mm per side 4. dimension e does not include interterminal mold protrusions or terminal protrusions. interminal mold protrusions and/or termin al protrusions shall not exceed 0.20mm per side 5. dimension b applies to plated terminals. dimension a1 is primarily y terminal plating, but may or may not include a small protrusion of terminal below the bottom surface of the package 6. burr shall not exceed 0.060mm 7. jedec mo-229 symbols dimensions in millimeters min. nom. max. a 0.81 0.9 1.00 a1 0 0.015 0.03 a3 ------ 0.20 ref ------ b 0.25 0.30 0.37 d 2.85 3.00 bsc 3.15 d1 ------ 2.3 bsc ------ e 2.85 3.00 bsc 3.15 e1 ------ 1.5 bsc ------ e ------ 0.65 bsc ----- l 0.25 0.35 0.45 aaa ------ 0.25 ------ bbb ------ 0.10 ------ ccc ------ 0.10 ------ m ------ ------ 0.05 -12 ------ 0 www.datasheet.in
EUA6204 ds6204 ver1.1 june. 2006 12 msop-8 note 1. package body sizes exclude mold flash and gate burrs 2. dimension l is measured in gage plane 3. tolerance 0.10mm unless otherwise specified 4. controlling dimension is millimeter. converted inch dimensions are not necessarily exact. dimensions in millimeters dimensions in inches symbols min. nom. max. min. nom. max. a 0.81 0.95 1.10 0.032 0.0375 0.043 a1 0.05 0.09 0.15 0.002 0.004 0.006 a2 0.76 0.86 0.97 0.030 0.034 0.038 b 0.28 0.30 0.38 0.011 0.012 0.015 c 0.13 0.15 0.23 0.005 0.006 0.009 d 2.90 3.00 3.10 0.114 0.118 0.122 e 4.70 4.90 5.10 0.185 0.193 0.201 e1 2.90 3.00 3.10 0.114 0.118 0.122 e ------ 0.65 ----- ------ 0.026 ------ l 0.40 0.53 0.66 0.016 0.021 0.026 y ------ ------ 0.10 ------ ------ 0.004 c 0 ------ 6 0 ------ 6 www.datasheet.in


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